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EM6A9160TSA
8M x 16 DDR Synchronous DRAM (SDRAM)
Advanced (Rev. 1.1 Aug. /2009)
Features
Fast clock rate: 250MHz Differential Clock CK & CK input Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 2M x 16-bit for each bank Programmable Mode and Extended Mode registers - CAS Latency: 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved * Individual byte write mask control * DM Write Latency = 0 * Auto Refresh and Self Refresh * 4096 refresh cycles / 64ms * Precharge & active power down * Power supplies: VDD & VDDQ = 2.5V 5% * Interface: SSTL_2 I/O Interface * Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb and Halogen Free * * * * * * * *
Table 1.Ordering Information
Clock Data Rate Package Frequency EM6A9160TSA-4G 250MHz 500Mbps/pin TSOPII Part Number TS: indicates TSOP II package A: indicates Generation Code G: indicates Pb and Halogen Free for TSOPII Package
Figure 1. Pin Assignment (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
Overview
The EM6A9160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK .Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM6A9160 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6A9160 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
EtronTech
Figure 2. Block Diagram
CK CK CKE
Row Decoder Row Decoder Row Decoder DQ Buffer Row Decoder DLL CLOCK BUFFER
EM6A9160TSA
CS RAS CAS WE
COMMAND DECODER
CONTROL SIGNAL GENERATOR
2M x 16 CELL ARRAY (BANK #0) Column Decoder
A10/AP
COLUMN COUNTER
MODE REGISTER
2M x 16 CELL ARRAY (BANK #1) Column Decoder
A0 A9 A11 BA0 BA1 LDQS UDQS DQ0 DQ15 ~ ~
ADDRESS BUFFER
REFRESH COUNTER
2M x 16 CELL ARRAY (BANK #2) Column Decoder
DATA STROBE BUFFER
2M x 16 CELL ARRAY (BANK #3) Column Decoder
LDM UDM
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Pin Descriptions Table 2. Pin Details of EM6A9160
Symbol CK, CK Type Input Description
EM6A9160TSA
Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGH" or "LOW". Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive edges of CK and CK . The I/Os are byte-maskable during Writes. Power Supply: +2.5V 5%
CKE
Input
BA0, BA1 A0-A11
Input Input
CS
Input
RAS
Input
CAS
Input
WE
Input
LDQS, UDQS LDM, UDM DQ0 - DQ15 VDD
Input / Output Input
Input / Output Supply
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VSS VDDQ VSSQ VREF NC Supply Supply Supply Supply Ground
EM6A9160TSA
DQ Power: +2.5V 5%. Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Reference Voltage for Inputs: +0.5*VDDQ No Connect: No internal connection, these pins suggest to be left unconnected.
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Operation Mode
Table 3 shows the truth table for the operation commands.
EM6A9160TSA
Table 3. Truth Table (Note (1), (2))
Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended MRS No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Data Input Mask Disable State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Idle Any Active(4) Any Idle Idle Idle
(SelfRefresh)
CKEn-1 H H H H H H H H H H H H H H L H L H L H
CKEn DM BA0,1 A10 A0-9,11 CS X X X X X X X X X X X X H L H L H L H X X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V Row address L L H L H L H X X
Column address (A0 ~ A8) Column address (A0 ~ A8)
RAS
CAS
WE
L L L H H H H L L H H X L L X H X H X H X V X H X X
H H H L L L L L L H H X L L X H X H X H X V X H X X
H L L L L H H L L H L X H H X H X H X H X V X H X X
L L L L L L L L
OP code OP code X X X X X X X X X X X X X X X X X X X X X X
L L H L L H L H L H L H L H L X
Idle Any
(PowerDown)
Active Any
(PowerDown)
Active
Data Input Mask Enable(5) Active H X H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 2, 4, and 8 burst operation. 5. LDM and UDM can be enabled respectively.
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Mode Register Set (MRS)
EM6A9160TSA
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
0
0
T.M.
CAS Latency
BT
Burst Length
Mode Register
A8 0 1 X
A7 Test Mode 0 Normal mode 0 DLL Reset 1 Test mode
BA0 Mode 0 MRS 1 EMRS
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 CAS Latency 0 Reserved 1 Reserved 0 Reserved 1 3 0 Reserved 1 Reserved 0 Reserved 1 Reserved
A3 Burst Type 0 Sequential 1 Interleave
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
* Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, and 8.
Table 5. Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
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Table 6. Addressing Mode
A3 0 1 * Addressing Mode Sequential Interleave
EM6A9160TSA
* Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4, and 8.
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 7. Burst Address ordering
Burst Length 2 Start Address A2 A1 A0 X X 0 X X 1 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
4
8
* CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) CAS Latency X tCK
Table 8. CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 clocks Reserved Reserved Reserved Reserved
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Table 9. Test Mode
A8 0 1 X * (BA0, BA1) A7 0 0 1 Test Mode Normal mode DLL Reset Test mode
EM6A9160TSA
* Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 10. MRS/EMRS
BA1 RFU RFU BA0 0 1 A11 ~ A0 MRS Cycle Extended Functions (EMRS)
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Extended Mode Register Set (EMRS)
EM6A9160TSA
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE . The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
1
RFU must be set to "0"
DS1 RFU must be set to "0" DS0 DLL Extended Mode Register
BA0 Mode 0 MRS 1 EMRS
A6 A1 Drive Strength Comment 0 0 Full 0 1 Weak 1 0 RFU Reserved For Future 1 1 Matched impedance Output driver matches impedance
A0 0 1
DLL Enable Disable
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Table 12. Absolute Maximum Rating
Symbol VIN, VOUT VIN VDD, VDDQ TA TSTG PD Item I/O Pins Voltage VREF and Inputs Voltage Power Supply Voltage Ambient Temperature Storage Temperature Power Dissipation Rating -4 - 0.5~VDDQ + 0.5 - 1~3.6 - 1~3.6 0~70 - 55~150 1
EM6A9160TSA
Unit V V V C C W
Note 1,2 1,2 1,2 1 1 1
IOUT Short Circuit Output Current 50 mA 1 Note1: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the devices Note2: These voltages are relative to Vss
Table 13. Recommended D.C. Operating Conditions (TA = 0 ~ 70 C)
Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Termination Voltage Input High Voltage (DC) Input Low Voltage (DC) Input Voltage Level, CK and CK inputs Input Leakage current Output Leakage current Output High Voltage Output Low Voltage Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) II IOZ VOH VOL Min. 2.375 2.375 0.49* VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 -5 -5 VTT + 0.76 Max. 2.625 2.625 0.51* VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 5 5 VTT - 0.76 Unit V V V V V V V A A V V IOH = -15.2 mA IOL = +15.2mA 1,2 Note 1,2 1,2
Table 14. Capacitance (VDD = 2.5V5%, f = 1MHz, TA = 25 C)
Symbol CIN1 Parameter Input Capacitance (CK, CK ) Min. 2 Max. 4 Unit pF
CIN2 Input Capacitance (All other input-only pins) 2 4 pF CI/O DQ, DQS, DM Input/Output Capacitance 4 6 pF Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested
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Table 15. D.C. Characteristics (VDD = 2.5V 5%, TA = 0~70 C)
Parameter & Test Condition Symbol OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (min); IDD0 tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing IDD1 once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; IDD2P power-down mode; tCK=tCK(min); CKE=LOW IDLE STANDLY CURRENT : CKE = HIGH; CS =HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; powerdown mode; CKE=LOW; tCK=tCK(min) IDD2N IDD3P
EM6A9160TSA
-4 Max. 130
Unit mA
150 15 50 40 90
mA mA mA mA mA
ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; IDD3N tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; IDD4R tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock IDD4W cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Self Refresh Mode ; CKE0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputschang only during Active, READ , or WRITE command IDD5 IDD6
190
mA
190
mA
210 6
mA mA
IDD7
310
mA
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Table 16. Electrical AC Characteristics (VDD = 2.5V 5%, TA = 0~70 C)
Symbol tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH tRC tRFC tRAS tRCD tRP tRRD tWR tMRD tCCD tDAL tXSRD tPDEX tREFI tIPW tDIPW tHZ tLZ tQHS tDSS tDSH tWTR tXSNR Clock cycle time Clock high level width Clock low level width DQS-out access time from CK, CK Output access time from CK, CK DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS write preamble DQS write postamble DQS in high level pulse width DQS in low level pulse width Address and Control input setup time Address and Control input hold time Fast slew rate Slow slew rate Fast slew rate Slow slew rate Parameter CL = 3 Min. 4 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.6 0.7 0.6 0.7 0.4 0.4 tCLMIN or tCHMIN tHP - tQHS 52 70 36 16 16 12 12 2 1 7 200 tCK + tIS 2.2 1.75 -0.7 0.2 0.2 2 75
EM6A9160TSA
-4 Max. 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 70K 15.6 0.7 0.7 0.4 Unit ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK
ns
DQ & DM setup time to DQS DQ & DM hold time to DQS Clock half period DQ/DQS output hold time from DQS Row cycle time Refresh row cycle time Row active time Active to Read or Write Delay Row precharge time Row active to Row active delay Write recovery time Mode register set cycle time Col. Address to Col. Address delay Auto precharge write recovery + Precharge time Self refresh exit to read command delay Power down exit time Refresh interval time Cntrol and Address input pulse width DQ & DM input pulse width (for each input) Data-out high-impedance window from CK, CK Data-out low-impedance window from CK, CK Data Hold Skew Factor DQS falling edge to CK rising - setup time DQS falling edge to CK rising - hold time Internal Write to Read command delay Exit Self-Refresh to non-Read command
ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK ns s ns ns ns ns ns tCK tCK tCK ns
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Parameter Input High Voltage (AC) Input Low Voltage (AC) Input Different Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH (AC) VIL (AC) VID (AC) VIX (AC) Min. VREF + 0.35 0.7 0.5*VDDQ-0.2
EM6A9160TSA
Max. VREF - 0.35 VDDQ + 0.6 0.5*VDDQ+0.2 Unit V V V V
Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V 5%, TA = 0~70 C)
Note: 1. All voltages are referenced to VSS. 2. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 3. Power-up sequence is described in Note 5. 4. A.C. Test Conditions
Table 18. SSTL _2 Interface
Reference Level of Output Signals (VREF) Output Load Input Signal Levels(VIH / VIL) Input Signals Slew Rate Reference Level of Input Signals 0.5 * VDDQ Reference to the Test Load VREF+0.35 V / VREF-0.35V 1 V/ns 0.5 * VDDQ
Figure 3. SSTL_2 A.C. Test Load 0.5 * VDDQ
50 DQ, DQS Z0=50 30pF
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5. Power up Sequence Power up must be performed in the following sequence.
EM6A9160TSA
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE "LOW". 2) Start clock and maintain stable condition for minimum 200s. 3) Issue a "NOP" command and keep CKE "HIGH" 4) Issue a "Precharge All" command. 5) Issue EMRS - enable DLL. 6) Issue MRS - reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS - with A8 to low to initialize the mode register.
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Timing Waveforms Figure 4. Activating a Specific Row in a Specific Bank
CK CK CKE CS
HIGH
EM6A9160TSA
RAS
CAS
WE
Address
RA
BA0,1
BA
RA=Row Address BA=Bank Address
Don't Care
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Figure 5. tRCD and tRRD Definition
CK CK
EM6A9160TSA
COMMAND
ACT
NOP
NOP
ACT
NOP
NOP
RD/WR
NOP
Address
Row
Row
Col
BA0,BA1
Bank A
Bank B
Bank B
tRRD
tRCD Don't Care
Figure 6. READ Command
CK CK CKE CS RAS CAS WE A0 - A8 A10
DIS AP
HIGH
CA
EN AP
BA0,1
BA
CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge
Don't Care
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Figure 7. Read Burst Required CAS Latencies (CL=3)
CK CK
EM6A9160TSA
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank A, Col n
CL=3
DQS DQ
DO n
DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n
Don't Care
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CK CK
EM6A9160TSA
Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=3)
COMMAND
READ
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col o
CL=3
DQS DQ
DO n DO o
DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device
Don't Care
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CK CK
EM6A9160TSA
Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=3)
COMMAND
READ
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
CL=3
Bank, Col o
DQS DQ DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o)
DO n DO o
Don't Care
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CK CK
EM6A9160TSA
Figure 10. Random Read Accesses Required CAS Latencies (CL=3)
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col o
Bank, Col p
Bank, Col q
CL=3
DQS DQ
DO n DO n' DO o DO o' DO p
DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks
Don't Care
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CK CK
EM6A9160TSA
Figure 11. Terminating a Read Burst Required CAS Latencies (CL=3)
COMMAND
READ
NOP
BST
NOP
NOP
NOP
ADDRESS
Bank A, Col n
CL=3
DQS DQ
DO n
DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n
Don't Care
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Figure 12. Read to Write Required CAS Latencies (CL=3)
CK CK COMMAND READ BST NOP NOP
EM6A9160TSA
WRITE
NOP
ADDRESS
Bank, Col n
CL=3
Bank, Col o
tDQSS min
DQS DQ
DO n DI o
DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order
Don't Care
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Figure 13. Read to Precharge Required CAS Latencies (CL=3)
CK CK
EM6A9160TSA
COMMAND
READ
NOP
PRE
NOP
NOP
ACT
tRP
ADDRESS
Bank A, Col n
Bank (a or all) Bank A, Row
CL=3
DQS DQ
DO n
DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met
Don't Care
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Figure 14. Write Command
CK CK CKE CS RAS CAS WE A0 - A8 A10
DIS AP
EM6A9160TSA
HIGH
CA
EN AP
BA0,1
BA
CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge
Don't Care
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Figure 15. Write Max DQSS
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
ADDRESS
Bank A, Col n
tDQSS max
DQS DQ DM DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled)
DI n
Don't Care
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Figure 16. Write Min DQSS
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
ADDRESS
Bank A, Col n tDQSS min
DQS DQ DM
DI n
DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled)
Don't Care
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Figure 17. Write Burst Nom, Min, and Max tDQSS
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank , Col n
tDQSS (nom)
DQS DQ
DI n
DM
tDQSS (min)
DQS DQ
DI n
DM
tDQSS (max)
DQS
DQ
DI n
DM
DI n = Data In for column n 3 subsequent elements of Data are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) DM=UDM & LDM
Don't Care
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Figure 18. Write to Write Max tDQSS
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
WRITE
NOP
NOP
NOP
ADDRESS
Bank , Col n
Bank , Col o
tDQSS (max)
DQS DQ
DI n DI o
DM DI n , etc. = Data In for column n,etc. 3 subsequent elements of Data In are applied in the programmed order following DI n 3 subsequent elements of Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= UDM & LDM
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Figure 19. Write to Write Max tDQSS, Non Consecutive
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
WRITE
NOP
NOP
ADDRESS
Bank Col n
Bank Col o
tDQSS (max)
DQS DQ
DI n DI o
DM
DI n, etc. = Data In for column n, etc. 3 subsequent elements of Data In are applied in the programmed order following DI n 3 subsequent elements of Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= UDM & LDM
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Figure 20. Random Write Cycles Max tDQSS
T0 CK CK COMMAND
WRITE WRITE WRITE WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE
ADDRESS
Bank Col n
Bank Col o
Bank Col p
Bank Col q
Bank Col r
tDQSS (max)
DQS DQ
DI n DI n DI o DI o DI p DI p DI q DI q
DM
DI n, etc. = Data In for column n, etc. n', etc. = the next Data In following DI n, etc. according to the programmed burst order Programmed Burst Length 2, 4, or 8 in cases shown If burst of 4 or 8, the burst would be truncated Each WRITE command may be to any bank and may be to the same or different devices DM= UDM & LDM
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Figure 21. Write to Read Max tDQSS Non Interrupting
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
tWTR
READ
NOP
ADDRESS
Bank Col n
Bank Col o
CL=3
tDQSS (max)
DQS DQ
DI n
DM DI n, etc. = Data In for column n, etc. 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown tWTR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= UDM & LDM
Don't Care
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Figure 22. Write to Read Max tDQSS Interrupting
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
NOP
NOP
NOP
tWTR
READ
NOP
ADDRESS
Bank Col n
Bank Col o
CL=3
tDQSS (max)
DQS DQ
DI n
DM DI n, etc. = Data In for column n, etc. 1 subsequent elements of Data In are applied in the programmed order following DI n An interrupted burst of 8 is shown, 2 data elements are written tWTR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= UDM & LDM
Don't Care
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T0 CK CK COMMAND
WRITE
EM6A9160TSA
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
NOP
NOP
NOP
tWTR
READ
NOP
NOP
ADDRESS
Bank Col n
Bank Col o
CL=3
tDQSS (max)
DQS DQ
DI n
DM
DI n = Data In for column n An interrupted burst of 8 is shown, 3 data elements are written tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired Data In element) A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= UDM & LDM
Don't Care
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Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
tWR
PRE
ADDRESS
Bank a, Col n
tDQSS (max)
Bank (a or al)
tRP
DQS DQ
DI n
DM
DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) DM= UDM & LDM
Don't Care
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Figure 25. Write to Precharge Max tDQSS, Interrupting
T0 CK CK COMMAND
WRITE
EM6A9160TSA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
tWR
PRE
Bank (a or all)
NOP
ADDRESS
Bank a, Col n
tDQSS (max) *2
tRP
DQS DQ DM
DI n
*1
*1
*1
*1
DI n = Data In for column n An interrupted burst of 4 or 8 is shown, 2 data elements are written tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point DM= UDM & LDM
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T0 CK CK COMMAND
WRITE
EM6A9160TSA
Figure 26. Write to Precharge Max tDQSS, ODD Number of Data Interrupting
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
NOP
NOP
NOP
tWR
PRE
NOP
ADDRESS
Bank a, Col n
Bank (a or all)
tDQSS (max)
*2
tRP
DQS DQ
DI n
DM
*1
*1
*1
*1
DI n = Data In for column n An interrupted burst of 4 or 8 is shown, 1 data element is written tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point DM= UDM & LDM
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Figure 27. Precharge Command
CK CK CKE CS RAS CAS WE A0-A9, A11
ALL BANKS
EM6A9160TSA
HIGH
A10
ONE BANK
BA0,1
BA BA= Bank Address (if A10 is LOW, otherwise don't care)
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Figure 28. Power-Down
T0 CK CK tIS CKE tIS T1 T2 T3 T4 Tn Tn+1 Tn+2
EM6A9160TSA
Tn+3 Tn+4 Tn+5 Tn+6
COMMAND
VALID
NOP
NOP
VALID
No column access in progress
Enter power-down mode
Exit power-down mode
Don't Care Figure 29. Clock Frequency Change in Precharge
T0
CK CK
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
CMD CKE
NOP
NOP
Frequency Change Occurs here
NOP
DLL RESET
NOP
NOP
Valid
tIS
tRP
Minmum 2 clocks Required before Changing frequency Stable new clock Before power down exit 200 Clocks
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Figure 30. Data input (Write) Timing
tDQSH DQS tDS DQ tDH tDS DM tDH DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n
DI n
EM6A9160TSA
tDQSL
Don't Care
Figure 31. Data Output (Read) Timing tCH
CK CK DQS
tCL
DQ
tDQSQ
max
tDQSQ tQH
max
tQH
Burst Length = 4 in the case shown
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Figure 32. Initialize and Mode Register Sets
VDD VDDQ
tVDT>=0
EM6A9160TSA
VTT (system*) VREF
tCK tCH tCL tIS tIH
CK CK
CKE
tIS tIH
COMMAND
NOP
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
DM
tIS tIH
A0-A9, A11
CODE
CODE
ALL BANKS
CODE
RA
ALL BANKS
tIS tIH
CODE CODE
A10
CODE
RA
tIS tIH
BA0,BA1
High-Z
tIS tIH
BA0=H BA1=L BA0=L BA1=L
tIS tIH
BA0=L BA1=L
BA
DQS DQ
T=200s High-Z **tMRD Extended mode Register set **tMRD tRP 200 cycles of CK** Load Mode Register, Reset DLL (with A8=H) Load Mode Register, (with A8=L) tRFC tRFC **tMRD
Power-up: VDD and CLK stable
*=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up **=tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command can be applied The two Auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL command
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Figure 33. Power Down Mode
tCK CK CK tIS tIH CKE tIS tIH COMMAND
VALID*
EM6A9160TSA
tCH
tCL
tIS
tIS
NOP
NOP
VALID
tIS tIH ADDR
VALID VALID
DQS
DQ
DM
Enter power-down mode
Exit power-down mode
No column accesses are allowed to be in progress at the time Power-Down is entered *=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is active Power Down.
Don't Care
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Figure 34. Auto Refresh Mode
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE VALID VALID
tIS tIH
COMMAND
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
ACT
A0-A8
RA
A9,A11
RA
ALL BANKS
A10
ONE BANKS
RA
tIS tIH
BA0,BA1
*Bank(s)
RA
DQS
DQ
DM tRP tRFC tRFC
* = Don't Care , if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC DM, DQ and DQS signals are all Don't Care /High-Z for operations shown
Don't Care
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Figure 35. Self Refresh Mode
tCK tCH CK CK tIS tIH CKE tIS tIH COMMAND
NOP Clock must be stable before Exiting Self Refresh mode
EM6A9160TSA
tCL
tIS
tIS
AR
NOP
VALID
tIS tIH ADDR
VALID
DQS
DQ
DM tXSNR/ tXSRD**
Exit Self Refresh mode
tRP*
Enter Self Refresh mode
* = Device must be in the All banks idle state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied.
Don't Care
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Figure 36. Read without Auto Precharge
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE
tIH
VALID VALID VALID
tIS tIH
COMMAND
NOP
READ
NOP
PRE
NOP
NOP
ACT
NOP
NOP
NOP
tIS tIH
A0-A8
Col n
RA
A9,A11 tIS A10
DIS AP ONE BANKS
RA
tIH
ALL BANKS
RA
tIS tIH
BA0,BA1 Bank X CL=3 DM Case 1: tAC/tDQSCK=min
*Bank X
Bank X tRP
tDQSCK tRPRE
DQS min
tRPST
tLZ
DQ
min
DO n
tLZ
Case 2: tAC/tDQSCK=max
min
tAC
min max
tDQSCK tRPRE
tRPST
DQS max DQ max DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point
tLZ
DO n
tHZ tAC
max
tLZ
max
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other commands may be valid at these times Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
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Figure 37. Read with Auto Precharge
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE
tIH
VALID VALID VALID
tIS tIH
COMMAND
NOP
READ
NOP
NOP
NOP
NOP
ACT
NOP
NOP
NOP
tIS tIH
A0-A8
Col n
RA
A9,A11
RA
EN AP
A10 tIS tIH
RA
tIS tIH
BA0,BA1 Bank X CL=3 DM Case 1: tAC/tDQSCK=min tRP Bank X
tDQSCK
min
tRPST
tRPRE
DQS
tLZ
min DO n
DQ
tLZ
Case 2: tAC/tDQSCK=max
min
tAC
min
tDQSCK
max
tRPST
tRPRE
DQS max DQ max DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other commands may be valid at these times The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ may not be issued prior to tRASmin (BL*tCK/2)
tLZ
DO n
tHZ tAC
max
tLZ
max
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Figure 38. Bank Read Access
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE
tIS tIH
COMMAND
NOP
ACT
NOP
NOP
NOP
READ
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
RA
Col n
RA
A9,A11
RA
tIS tIH
RA
ALL BANKS
A10
RA
DIS AP ONE BANKS
RA
tIS tIH
BA0,BA1
Bank X Bank X
*Bank X
Bank X
tRC tRAS tRCD
DM Case 1: tAC/tDQSCK=min CL=3
tRP
tDQSCK tRPRE
DQS min
tRPST
DQ
min
tLZ
DO n min
tLZ
Case 2: tAC/tDQSCK=max DQS max DQ
min
tAC tDQSCK
max
tRPRE tLZ
tRPST tHZ
max DO n max
tLZ
DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
max
tAC
Don't Care
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Figure 39. Write without Auto Precharge
tCK
CK CK
EM6A9160TSA
tCH tCL
tIH
VALID
tIS tIH
CKE
tIS tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
Col n
RA
A9,A11 tIS tIH A10
DIS AP ONE BANKS
RA
ALL BANKS
RA
tIS tIH
BA0,BA1 Bank X
*Bank X
BA
Case 1: tDQSS=min DQS
tDQSS
tDSH tDQSH
tDSH
tRP tWR
tWPST
tWPRES
tDQSL
DI n
tWPRE
DQ
DM
tDSS
Case 2: tDQSS=max DQS
tDSS tWPST
tDQSS
tWPRES tWPRE
tDQSH
tDQSL
DI n
DQ
DM DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don't Care
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Figure 40. Write with Auto Precharge
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE VALID VALID VALID
tIS tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
tIS tIH
A0-A8
Col n
RA
A9,A11
RA
DIS AP
A10 tIS tIH BA0,BA1 Bank X
RA
BA
tDAL
Case 1: tDQSS=min DQS
tDQSS
tDSH tDQSH
tDSH
tWPST
tWPRES
tWPRE
DQ
DI n
tDQSL
DM
Case 2: tDQSS=max DQS
tDQSS
tDSS tDQSH
tDSS
tWPST
tWPRES tWPRE
DQ
DI n
tDQSL
DM
DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge
Don't Care
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Figure 41. Bank Write Access
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE
tIS tIH
COMMAND
NOP
ACT
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
tIS tIH
A0-A8
RA
Col n
A9,A11
RA
tIS tIH
ALL BANKS
A10
RA
DIS AP ONE BANK
tIS tIH BA0,BA1 Bank X Bank X
*Bank X
tRAS tRCD
Case 1: tDQSS=min DQS
tWR tDSH tDQSS tDQSH tDSH tWPST
tWPRES tWPRE
DQ
DI n
tDQSL
DM
Case 2: tDQSS=max DQS
tDSS tDQSS tDQSH tDSS tWPST tDQSL
tWPRE
DI n
tWPRES
DQ
DM
DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don't Care
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Figure 42. Write DM Operation
tCK
CK CK
EM6A9160TSA
tCH tCL
tIS tIH
CKE VALID
tIS tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A8
Col n
RA
A9,A11 tIS tIH A10
DIS AP ONE BANKS
RA
ALL BANKS
RA
tIS tIH
BA0,BA1 Case 1: tDQSS=min DQS Bank X
*Bank X
BA
tDQSS
tDSH tDQSH
tDSH
tRP tWPST tWR
tWPRES
tDQSL
DI n
tWPRE
DQ
DM
tDSS
Case 2: tDQSS=max DQS
tDSS tWPST
tDQSS
tWPRES tWPRE
tDQSH
tDQSL
DI n
DQ
DM
DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don't Care
Etron Confidential
50
Rev. 1.1
Aug. 2009
EtronTech
Figure 43. 66 Pin TSOP II Package Outline Drawing Information: Units: mm
D
EM6A9160TSA
C
C
HE
E
A2
L A1 S e b A F
(TYP)
Symbol A A1 A2 b e C D E HE L L1 F S
Dimension in mm Min Nom Max
--0.05 0.9 0.22 --0.095 22.09 10.03 11.56 0.40 ----0 --------1.0 --0.65 0.125 22.22 10.16 11.76 0.5 0.8 0.25 --0.71 --1.2 0.2 1.1 0.45 --0.21 22.35 10.29 11.96 0.6 ----8 --0.10
Dimension in inch Min Nom Max
--0.002 0.035 0.009 --0.004 0.87 0.395 0.455 0.016 ----0 --------0.039 --0.026 0.005 0.875 0.4 0.463 0.02 0.032 0.01 --0.028 --0.047 0.008 0.043 0.018 --0.008 0.88 0.405 0.471 0.024 ----8 --0.004
y
Etron Confidential
D
51
Rev. 1.1
Aug. 2009
L1

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